Field
Embodiments of the present disclosure generally relate to the field of maskless lithography and more specifically to reducing measurement error of an actual location of alignment mark and/or feature on a substrate.
Description of the Related Art
Microlithography techniques are generally employed to create electrical features on a substrate. A light-sensitive photoresist is typically applied to at least one surface of the substrate. Then, either a photolithography mask or pattern generator like a micro-mirror array exposes selected areas of the light-sensitive photoresist as part of a pattern. Light causes chemical changes to the photoresist in the selected areas to prepare these selected areas for subsequent material removal and/or material addition processes to create the electrical features. The precise placement of the electrical features upon the substrate determines the quality of the electrical interconnections.
Alignment techniques are implemented during manufacturing processes to ensure correct alignment of the various layers with one another. Typically, alignment marks are utilized in the layers to assist in the alignment of features in different layers. An increased accuracy in identification of a location of the alignment mark(s) may provide a more accurate alignment of the layers and therefore reduction in overlay error.
Therefore, there is a need in the art for increased accuracy in aligning layers.